8:19 p.m.
Hi John,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.4-rc5 next-20191031]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/John-Garry/lib-logic_pio-Enforce...
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
23fdb198ae81f47a574296dab5167c5e136a02ba
config: parisc-allmodconfig (attached as .config)
compiler: hppa-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=parisc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
drivers//bus/hisi_lpc.c: In function 'hisi_lpc_target_in':
> drivers//bus/hisi_lpc.c:137:2: error: implicit declaration of
function 'readsb'; did you mean 'readb'?
[-Werror=implicit-function-declaration]
readsb(lpcdev->membase +
LPC_REG_RDATA, buf, opcnt);
^~~~~~
readb
drivers//bus/hisi_lpc.c: In function 'hisi_lpc_target_out':
> drivers//bus/hisi_lpc.c:180:2: error: implicit declaration of
function 'writesb'; did you mean 'writeb'?
[-Werror=implicit-function-declaration]
writesb(lpcdev->membase +
LPC_REG_WDATA, buf, opcnt);
^~~~~~~
writeb
cc1: some warnings being treated as errors
vim +137 drivers//bus/hisi_lpc.c
adf38bb0b5956a Zhichang Yuan 2018-03-21 90
adf38bb0b5956a Zhichang Yuan 2018-03-21 91 /*
adf38bb0b5956a Zhichang Yuan 2018-03-21 92 * hisi_lpc_target_in - trigger a series of
LPC cycles for read operation
adf38bb0b5956a Zhichang Yuan 2018-03-21 93 * @lpcdev: pointer to hisi lpc device
adf38bb0b5956a Zhichang Yuan 2018-03-21 94 * @para: some parameters used to control
the lpc I/O operations
adf38bb0b5956a Zhichang Yuan 2018-03-21 95 * @addr: the lpc I/O target port address
adf38bb0b5956a Zhichang Yuan 2018-03-21 96 * @buf: where the read back data is stored
adf38bb0b5956a Zhichang Yuan 2018-03-21 97 * @opcnt: how many I/O operations required,
i.e. data width
adf38bb0b5956a Zhichang Yuan 2018-03-21 98 *
adf38bb0b5956a Zhichang Yuan 2018-03-21 99 * Returns 0 on success, non-zero on fail.
adf38bb0b5956a Zhichang Yuan 2018-03-21 100 */
adf38bb0b5956a Zhichang Yuan 2018-03-21 101 static int hisi_lpc_target_in(struct
hisi_lpc_dev *lpcdev,
adf38bb0b5956a Zhichang Yuan 2018-03-21 102 struct lpc_cycle_para *para,
unsigned long addr,
adf38bb0b5956a Zhichang Yuan 2018-03-21 103 unsigned char *buf, unsigned long
opcnt)
adf38bb0b5956a Zhichang Yuan 2018-03-21 104 {
adf38bb0b5956a Zhichang Yuan 2018-03-21 105 unsigned int cmd_word;
adf38bb0b5956a Zhichang Yuan 2018-03-21 106 unsigned int waitcnt;
adf38bb0b5956a Zhichang Yuan 2018-03-21 107 unsigned long flags;
adf38bb0b5956a Zhichang Yuan 2018-03-21 108 int ret;
adf38bb0b5956a Zhichang Yuan 2018-03-21 109
adf38bb0b5956a Zhichang Yuan 2018-03-21 110 if (!buf || !opcnt || !para ||
!para->csize || !lpcdev)
adf38bb0b5956a Zhichang Yuan 2018-03-21 111 return -EINVAL;
adf38bb0b5956a Zhichang Yuan 2018-03-21 112
adf38bb0b5956a Zhichang Yuan 2018-03-21 113 cmd_word = 0; /* IO mode, Read */
adf38bb0b5956a Zhichang Yuan 2018-03-21 114 waitcnt = LPC_PEROP_WAITCNT;
adf38bb0b5956a Zhichang Yuan 2018-03-21 115 if (!(para->opflags &
FG_INCRADDR_LPC)) {
adf38bb0b5956a Zhichang Yuan 2018-03-21 116 cmd_word |= LPC_REG_CMD_SAMEADDR;
adf38bb0b5956a Zhichang Yuan 2018-03-21 117 waitcnt = LPC_MAX_WAITCNT;
adf38bb0b5956a Zhichang Yuan 2018-03-21 118 }
adf38bb0b5956a Zhichang Yuan 2018-03-21 119
adf38bb0b5956a Zhichang Yuan 2018-03-21 120 /* whole operation must be atomic */
adf38bb0b5956a Zhichang Yuan 2018-03-21 121
spin_lock_irqsave(&lpcdev->cycle_lock, flags);
adf38bb0b5956a Zhichang Yuan 2018-03-21 122
adf38bb0b5956a Zhichang Yuan 2018-03-21 123 writel_relaxed(opcnt, lpcdev->membase +
LPC_REG_OP_LEN);
adf38bb0b5956a Zhichang Yuan 2018-03-21 124 writel_relaxed(cmd_word, lpcdev->membase
+ LPC_REG_CMD);
adf38bb0b5956a Zhichang Yuan 2018-03-21 125 writel_relaxed(addr, lpcdev->membase +
LPC_REG_ADDR);
adf38bb0b5956a Zhichang Yuan 2018-03-21 126
adf38bb0b5956a Zhichang Yuan 2018-03-21 127 writel(LPC_REG_STARTUP_SIGNAL_START,
adf38bb0b5956a Zhichang Yuan 2018-03-21 128 lpcdev->membase +
LPC_REG_STARTUP_SIGNAL);
adf38bb0b5956a Zhichang Yuan 2018-03-21 129
adf38bb0b5956a Zhichang Yuan 2018-03-21 130 /* whether the operation is finished */
adf38bb0b5956a Zhichang Yuan 2018-03-21 131 ret = wait_lpc_idle(lpcdev->membase,
waitcnt);
adf38bb0b5956a Zhichang Yuan 2018-03-21 132 if (ret) {
adf38bb0b5956a Zhichang Yuan 2018-03-21 133
spin_unlock_irqrestore(&lpcdev->cycle_lock, flags);
adf38bb0b5956a Zhichang Yuan 2018-03-21 134 return ret;
adf38bb0b5956a Zhichang Yuan 2018-03-21 135 }
adf38bb0b5956a Zhichang Yuan 2018-03-21 136
adf38bb0b5956a Zhichang Yuan 2018-03-21 @137 readsb(lpcdev->membase + LPC_REG_RDATA,
buf, opcnt);
adf38bb0b5956a Zhichang Yuan 2018-03-21 138
adf38bb0b5956a Zhichang Yuan 2018-03-21 139
spin_unlock_irqrestore(&lpcdev->cycle_lock, flags);
adf38bb0b5956a Zhichang Yuan 2018-03-21 140
adf38bb0b5956a Zhichang Yuan 2018-03-21 141 return 0;
adf38bb0b5956a Zhichang Yuan 2018-03-21 142 }
adf38bb0b5956a Zhichang Yuan 2018-03-21 143
adf38bb0b5956a Zhichang Yuan 2018-03-21 144 /*
adf38bb0b5956a Zhichang Yuan 2018-03-21 145 * hisi_lpc_target_out - trigger a series of
LPC cycles for write operation
adf38bb0b5956a Zhichang Yuan 2018-03-21 146 * @lpcdev: pointer to hisi lpc device
adf38bb0b5956a Zhichang Yuan 2018-03-21 147 * @para: some parameters used to control
the lpc I/O operations
adf38bb0b5956a Zhichang Yuan 2018-03-21 148 * @addr: the lpc I/O target port address
adf38bb0b5956a Zhichang Yuan 2018-03-21 149 * @buf: where the data to be written is
stored
adf38bb0b5956a Zhichang Yuan 2018-03-21 150 * @opcnt: how many I/O operations required,
i.e. data width
adf38bb0b5956a Zhichang Yuan 2018-03-21 151 *
adf38bb0b5956a Zhichang Yuan 2018-03-21 152 * Returns 0 on success, non-zero on fail.
adf38bb0b5956a Zhichang Yuan 2018-03-21 153 */
adf38bb0b5956a Zhichang Yuan 2018-03-21 154 static int hisi_lpc_target_out(struct
hisi_lpc_dev *lpcdev,
adf38bb0b5956a Zhichang Yuan 2018-03-21 155 struct lpc_cycle_para *para,
unsigned long addr,
adf38bb0b5956a Zhichang Yuan 2018-03-21 156 const unsigned char *buf, unsigned
long opcnt)
adf38bb0b5956a Zhichang Yuan 2018-03-21 157 {
adf38bb0b5956a Zhichang Yuan 2018-03-21 158 unsigned int waitcnt;
adf38bb0b5956a Zhichang Yuan 2018-03-21 159 unsigned long flags;
adf38bb0b5956a Zhichang Yuan 2018-03-21 160 u32 cmd_word;
adf38bb0b5956a Zhichang Yuan 2018-03-21 161 int ret;
adf38bb0b5956a Zhichang Yuan 2018-03-21 162
adf38bb0b5956a Zhichang Yuan 2018-03-21 163 if (!buf || !opcnt || !para || !lpcdev)
adf38bb0b5956a Zhichang Yuan 2018-03-21 164 return -EINVAL;
adf38bb0b5956a Zhichang Yuan 2018-03-21 165
adf38bb0b5956a Zhichang Yuan 2018-03-21 166 /* default is increasing address */
adf38bb0b5956a Zhichang Yuan 2018-03-21 167 cmd_word = LPC_REG_CMD_OP; /* IO mode,
write */
adf38bb0b5956a Zhichang Yuan 2018-03-21 168 waitcnt = LPC_PEROP_WAITCNT;
adf38bb0b5956a Zhichang Yuan 2018-03-21 169 if (!(para->opflags &
FG_INCRADDR_LPC)) {
adf38bb0b5956a Zhichang Yuan 2018-03-21 170 cmd_word |= LPC_REG_CMD_SAMEADDR;
adf38bb0b5956a Zhichang Yuan 2018-03-21 171 waitcnt = LPC_MAX_WAITCNT;
adf38bb0b5956a Zhichang Yuan 2018-03-21 172 }
adf38bb0b5956a Zhichang Yuan 2018-03-21 173
adf38bb0b5956a Zhichang Yuan 2018-03-21 174
spin_lock_irqsave(&lpcdev->cycle_lock, flags);
adf38bb0b5956a Zhichang Yuan 2018-03-21 175
adf38bb0b5956a Zhichang Yuan 2018-03-21 176 writel_relaxed(opcnt, lpcdev->membase +
LPC_REG_OP_LEN);
adf38bb0b5956a Zhichang Yuan 2018-03-21 177 writel_relaxed(cmd_word, lpcdev->membase
+ LPC_REG_CMD);
adf38bb0b5956a Zhichang Yuan 2018-03-21 178 writel_relaxed(addr, lpcdev->membase +
LPC_REG_ADDR);
adf38bb0b5956a Zhichang Yuan 2018-03-21 179
adf38bb0b5956a Zhichang Yuan 2018-03-21 @180 writesb(lpcdev->membase + LPC_REG_WDATA,
buf, opcnt);
adf38bb0b5956a Zhichang Yuan 2018-03-21 181
adf38bb0b5956a Zhichang Yuan 2018-03-21 182 writel(LPC_REG_STARTUP_SIGNAL_START,
adf38bb0b5956a Zhichang Yuan 2018-03-21 183 lpcdev->membase +
LPC_REG_STARTUP_SIGNAL);
adf38bb0b5956a Zhichang Yuan 2018-03-21 184
adf38bb0b5956a Zhichang Yuan 2018-03-21 185 /* whether the operation is finished */
adf38bb0b5956a Zhichang Yuan 2018-03-21 186 ret = wait_lpc_idle(lpcdev->membase,
waitcnt);
adf38bb0b5956a Zhichang Yuan 2018-03-21 187
adf38bb0b5956a Zhichang Yuan 2018-03-21 188
spin_unlock_irqrestore(&lpcdev->cycle_lock, flags);
adf38bb0b5956a Zhichang Yuan 2018-03-21 189
adf38bb0b5956a Zhichang Yuan 2018-03-21 190 return ret;
adf38bb0b5956a Zhichang Yuan 2018-03-21 191 }
adf38bb0b5956a Zhichang Yuan 2018-03-21 192
:::::: The code at line 137 was first introduced by commit
:::::: adf38bb0b5956ab5469acb1ca981a9287c7ad1d8 HISI LPC: Support the LPC host on
Hip06/Hip07 with DT bindings
:::::: TO: Zhichang Yuan <yuanzhichang(a)hisilicon.com>
:::::: CC: Bjorn Helgaas <helgaas(a)kernel.org>
---
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