[PATCH V0] linux-yocto-efi-test: Use custom LINUX_VERSION_EXTENSION
by Megha Dey
Poky has recently made the LINUX_VERSION_EXTENSION weaker in commit
9cc5cf0a64d("linux-yocto: Make LINUX_VERSION_EXTENSION weaker").
Use the custom LUV kernel extension in the LUV kernel recipe to remove
the actual nvdimm drivers and keep only the testing drivers.
Signed-off-by: Megha Dey <megha.dey(a)linux.intel.com>
---
meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
index faa9c6a..38d635e 100644
--- a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
+++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
@@ -124,8 +124,8 @@ KCONFIG_MODE = 'alldefconfig'
KBUILD_DEFCONFIG = "defconfig"
KBUILD_DEFCONFIG_x86 = "i386_defconfig"
KBUILD_DEFCONFIG_x86-64 = "x86_64_defconfig"
-LINUX_VERSION ?= "4.14"
-LINUX_VERSION_EXTENSION ?= "-efitest"
+LINUX_VERSION = "4.14"
+LINUX_VERSION_EXTENSION = "-efitest"
# Override SRCREV to point to a different commit in a bbappend file to
# build a different release of the Linux kernel.
@@ -143,8 +143,8 @@ do_install_append() {
if [ "${TARGET_ARCH}" = "x86_64" ]; then
# There are 2 copies of the NVDIMM modules which are built. This is a
# temporary fix to make sure the correct set of modules are used.
- rm -rf ${D}/lib/modules/${LINUX_VERSION}.0-yocto-standard/kernel/drivers/nvdimm/
- rm -rf ${D}/lib/modules/${LINUX_VERSION}.0-yocto-standard/kernel/drivers/dax/
- rm -rf ${D}/lib/modules/${LINUX_VERSION}.0-yocto-standard/kernel/drivers/acpi/
+ rm -rf ${D}/lib/modules/${LINUX_VERSION}.0${LINUX_VERSION_EXTENSION}/kernel/drivers/nvdimm/
+ rm -rf ${D}/lib/modules/${LINUX_VERSION}.0${LINUX_VERSION_EXTENSION}/kernel/drivers/dax/
+ rm -rf ${D}/lib/modules/${LINUX_VERSION}.0${LINUX_VERSION_EXTENSION}/kernel/drivers/acpi/
fi
}
--
1.9.1
3 years, 8 months
[PATCH 2/3] AArch64: Build grub-efi v2.02 for AArch64
by Naresh Bhat
We are trying to build and use grub across x86/ARM64 architecture.
Earlier there was no support of AArch64 in grub-efi, Hence AArch64
was dependent on upstream grub git repository. The LUV project use
to pull and build grub git repository whenever we build the project
for AArch64. But recently poky updated meta layer with grub v2.02
and LUV is rebased on top of poky. Hence we can use a common grub
across all the architecture. The luv-netboot-image also depends on
the _RDEPENDS variable.
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
---
meta-luv/classes/luv-efi.bbclass | 12 +-----------
meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend | 12 ++++++++++--
meta-luv/recipes-core/images/luv-netboot-image.bb | 2 +-
meta/recipes-bsp/grub/grub-efi_2.02.bb | 3 +++
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/meta-luv/classes/luv-efi.bbclass b/meta-luv/classes/luv-efi.bbclass
index 441ab39..db7c886 100644
--- a/meta-luv/classes/luv-efi.bbclass
+++ b/meta-luv/classes/luv-efi.bbclass
@@ -16,17 +16,7 @@ def get_bits_depends(d):
return ""
_BITSDEPENDS = "${@get_bits_depends(d)}"
-# The x86 build is depends on grub-efi and AArch64 build depends on grub_git
-def get_grub_depends(d):
- import re
- deps = d.getVar('TARGET_PREFIX', True)
- if re.search("(x86_64|i.86).*",deps):
- return "${MLPREFIX}grub-efi"
- if re.search("aarch64",deps):
- return "${MLPREFIX}grub"
-
-_RDEPENDS = "${@get_grub_depends(d)}"
-do_bootimg[depends] += "${_RDEPENDS}:do_deploy \
+do_bootimg[depends] += "${MLPREFIX}grub-efi:do_deploy \
sbsigntool-native:do_populate_sysroot"
GRUB_EFI_LOADER_IMAGE_x86-64 = "grub-efi-bootx64.efi"
diff --git a/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend b/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
index de68f3d..3c11924 100644
--- a/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
+++ b/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
@@ -13,7 +13,7 @@ python __anonymous(){
d.appendVar("GRUB_BUILDIN", ' memdisk -m ${GRUB_MEMDISK}')
}
-SRC_URI += "file://0001-pe32.h-add-header-structures-for-TE-and-DOS-executab.patch \
+COMMON_GRUB_x86 += "file://0001-pe32.h-add-header-structures-for-TE-and-DOS-executab.patch \
file://0002-shim-add-needed-data-structures.patch \
file://0003-efi-chainloader-implement-an-UEFI-Exit-service-for-s.patch \
file://0004-efi-chainloader-port-shim-to-grub.patch \
@@ -26,7 +26,15 @@ SRC_URI += "file://0001-pe32.h-add-header-structures-for-TE-and-DOS-executab.pat
file://0011-grub-core-loader-extend-loader-options.patch \
file://0012-grub-core-loader-add-support-for-memdisks.patch \
file://0013-grub-core-loader-pass-current-disk-device-to-loaded-.patch \
- file://0014-grub-util-set-prefix-to-EFI-BOOT-when-booting-f.patch \
+ "
+
+# Add grub-efi patches for x86/x86-64/arm64
+SRC_URI_append_x86 = "${COMMON_GRUB_x86} \
+ "
+SRC_URI_append_x86-64 = "${COMMON_GRUB_x86} \
+ "
+
+SRC_URI += "file://0014-grub-util-set-prefix-to-EFI-BOOT-when-booting-f.patch \
"
GRUB_BUILDIN = "boot linux ext2 fat serial part_msdos part_gpt \
diff --git a/meta-luv/recipes-core/images/luv-netboot-image.bb b/meta-luv/recipes-core/images/luv-netboot-image.bb
index 88381a7..26b18c2 100644
--- a/meta-luv/recipes-core/images/luv-netboot-image.bb
+++ b/meta-luv/recipes-core/images/luv-netboot-image.bb
@@ -64,4 +64,4 @@ addtask do_deploy before do_build after do_mkimage
addtask image_ext4 before do_bootimg before do_build
do_mkimage[depends] += "${INITRD_IMAGE_LIVE}:do_build"
-do_deploy[depends] += "${_RDEPENDS}:do_deploy"
+do_deploy[depends] += "${MLPREFIX}grub-efi:do_deploy"
diff --git a/meta/recipes-bsp/grub/grub-efi_2.02.bb b/meta/recipes-bsp/grub/grub-efi_2.02.bb
index b949beb..fa9c6a9 100644
--- a/meta/recipes-bsp/grub/grub-efi_2.02.bb
+++ b/meta/recipes-bsp/grub/grub-efi_2.02.bb
@@ -21,6 +21,9 @@ python __anonymous () {
elif re.match('i.86', target):
grubtarget = 'i386'
grubimage = "grub-efi-bootia32.efi"
+ elif re.match('aarch64', target):
+ grubtarget = 'arm64'
+ grubimage = "grub-efi-bootaa64.efi"
else:
raise bb.parse.SkipPackage("grub-efi is incompatible with target %s" % target)
d.setVar("GRUB_TARGET", grubtarget)
--
2.7.4
3 years, 10 months
[PATCH] linux-yocto-efi-test: Increase number of CPUS
by Naresh Bhat
Increase number of CPUs in linux yocto efi test kernel. The
Dual socket server machines will be having more number of CPUs
i.e for example 296, 224..etc. Hence increase the number of CPUs to
512. Without this patch all CPUs can't bought up while booting the
machine. Testing the LUV on those machines will be a weired behaviour
i.e. you can also possibly observe some crash, repeated messages
printing on console..etc.
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
---
meta-luv/recipes-kernel/linux/linux-yocto-efi-test/cpus.cfg | 1 +
meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb | 1 +
2 files changed, 2 insertions(+)
create mode 100644 meta-luv/recipes-kernel/linux/linux-yocto-efi-test/cpus.cfg
diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/cpus.cfg b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/cpus.cfg
new file mode 100644
index 0000000..9ce2b2d
--- /dev/null
+++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/cpus.cfg
@@ -0,0 +1 @@
+CONFIG_NR_CPUS=512
diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
index faa9c6a..5900e9e 100644
--- a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
+++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
@@ -109,6 +109,7 @@ SRC_URI_append_aarch64 = " file://qemuarm64/network.cfg \
SRC_URI_append = "file://pstore.cfg \
file://pstore-test.cfg \
file://efi.cfg \
+ file://cpus.cfg \
"
# Override KCONFIG_MODE to '--alldefconfig' from the default '--allnoconfig'
--
2.7.4
3 years, 10 months
[PATCH v2] bits_git.bb: Add a new file that includes the new unittest in BITS
by Gayatri Kammela
Machine Check Errors (MCE) test is added to BITS to find any errors
generated by the hardware or any specific subsystem(s). These errors
are often referred as a bank and number of banks is CPU dependent.
Each bank consists of a group of four MSRs(that we are interested
in)such as CTRL, STATUS, ADDR, MISC registers. CTRL MSR allows to
enable/disable the reporting of certain errors. STATUS MSR contains the
bits such as VAL(63)if set to 1 i.e., error occurred in this group and
if the third or fourth MSRs contain valid values.
The ADDR MSR contains the address of the failure. The value read out of
the MSR is only valid if only the status MSR reports valid. The
fourth(MISC) MSR contains misc information. It contains model specific
error codes which may vary even between the CPU models.
The tests focus on verifying if these bits in STATUS MSR are valid:
Bit 63 VAL — MCi_STATUS register valid
Bit 59 MISCV — MCi_MISC register valid
Bit 58 ADDRV — MCi_ADDR register valid (i is cpu dependent)
whereas the test results will log these details:
Physical CPU number
Global status register(also known as capability register)
Bank number(i)
Bank status register
Bank address register
Bank miscellaneous register
The Bank address register and bank miscellaneous register will be logged
only in case of occurrence of errors(mce).
The unittest reports "passed" always and reports "failure" in case of
occurrence of errors. This unittest is very unlikely to "skip" unless
the architecture does not support it.
Cc: Tony Luck <tony.luck(a)intel.com>
Cc: Ricardo Neri <ricardo.neri(a)intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela(a)intel.com>
---
test results of mce:
==== MCE tests ====
CPU 0 MSR 0x179: 0xc07
CPU 1 MSR 0x179: 0xc07
CPU 2 MSR 0x179: 0xc07
CPU 3 MSR 0x179: 0xc07
Detected 7 banks using MCG_CAP = 0xc07
CPU 0x0 MSR 0x401: 0x0
CPU 0x1 MSR 0x401: 0x0
CPU 0x2 MSR 0x401: 0x0
CPU 0x3 MSR 0x401: 0x0
CPU 0x0 MSR 0x405: 0x0
:
:
Summary: 7 passed, 0 failed
Changes since v1:
1) Remove additional tests within mce regarding the misc and addr register values
...t.py-Add-a-new-unittest-MCE-tests-to-BITS.patch | 161 +++++++++++++++++++++
meta-luv/recipes-bsp/bits/bits_git.bb | 1 +
2 files changed, 162 insertions(+)
create mode 100644 meta-luv/recipes-bsp/bits/bits/BITS-init.py-Add-a-new-unittest-MCE-tests-to-BITS.patch
diff --git a/meta-luv/recipes-bsp/bits/bits/BITS-init.py-Add-a-new-unittest-MCE-tests-to-BITS.patch b/meta-luv/recipes-bsp/bits/bits/BITS-init.py-Add-a-new-unittest-MCE-tests-to-BITS.patch
new file mode 100644
index 000000000000..995a911fac11
--- /dev/null
+++ b/meta-luv/recipes-bsp/bits/bits/BITS-init.py-Add-a-new-unittest-MCE-tests-to-BITS.patch
@@ -0,0 +1,161 @@
+From c3058924fc7a9bc93ccbb84387904947d837a183 Mon Sep 17 00:00:00 2001
+From: Gayatri Kammela <gayatri.kammela(a)intel.com>
+Date: Wed, 29 Nov 2017 14:29:38 -0800
+Subject: [PATCH] BITS/init.py: Add a new unittest "MCE tests" to BITS
+
+Machine check errors are reported by the hardware via internal registers
+called Model Specific Registers (MSRs). "rdmsr" is used to read these
+registers to determine if machine check errors (MCEs) are found.
+
+Add this new unittest to BITS, to find MCEs in the preboot environment.
+
+Cc: Tony Luck <tony.luck(a)intel.com>
+Cc: Ricardo Neri <ricardo.neri(a)intel.com>
+Signed-off-by: Gayatri Kammela <gayatri.kammela(a)intel.com>
+---
+ python/init.py | 5 +++
+ python/testmce.py | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 121 insertions(+)
+ create mode 100644 python/testmce.py
+
+diff --git a/python/init.py b/python/init.py
+index 73df14e6c6ea..803d2f292662 100644
+--- a/python/init.py
++++ b/python/init.py
+@@ -185,6 +185,11 @@ def init():
+ with init_annotation("testsmrr"):
+ testsmrr.register_tests()
+
++ with import_annotation("testmce"):
++ import testmce
++ with init_annotation("testmce"):
++ testmce.register_tests()
++
+ with import_annotation("smilatency"):
+ import smilatency
+ with init_annotation("smilatency"):
+diff --git a/python/testmce.py b/python/testmce.py
+new file mode 100644
+index 000000000000..458768c04100
+--- /dev/null
++++ b/python/testmce.py
+@@ -0,0 +1,116 @@
++# Copyright (c) 2017, Intel Corporation
++# All rights reserved.
++#
++# Redistribution and use in source and binary forms, with or without
++# modification, are permitted provided that the following conditions are met:
++#
++# * Redistributions of source code must retain the above copyright notice,
++# this list of conditions and the following disclaimer.
++# * Redistributions in binary form must reproduce the above copyright notice,
++# this list of conditions and the following disclaimer in the documentation
++# and/or other materials provided with the distribution.
++# * Neither the name of Intel Corporation nor the names of its contributors
++# may be used to endorse or promote products derived from this software
++# without specific prior written permission.
++#
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
++# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
++# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++
++""" Machine Check Errors. """
++
++import bits
++import bits.cdata
++import testsuite
++from cpudetect import cpulib
++from ctypes import c_ulong as ul
++import struct
++
++cpulist = sorted(bits.cpus())
++
++""" Global_CAP, Bank_STATUS, Bank_ADDR and Bank_MISC registers """
++MSR_IA32_MCG_CAP = 0x00000179
++MSR_IA32_MC0_STATUS = 0x00000401
++MSR_IA32_MC0_ADDR = 0x00000402
++MSR_IA32_MC0_MISC = 0x00000403
++
++def register_tests():
++ testsuite.add_test("MCE tests", test_mce);
++
++class IA32_MCi_bits(bits.cdata.Struct):
++ _fields_ = [
++ ('low', ul, 32),
++ ('high', ul, 32),
++ ]
++
++class IA32_MCi(bits.cdata.Union):
++ _anonymous_ = ('bits',)
++ _fields_ = [
++ ('u64', ul),
++ ('bits', IA32_MCi_bits),
++ ]
++
++def ia32_rdmsr(msr):
++ for cpu in cpulist:
++ ia32_mci_value = IA32_MCi(bits.rdmsr(cpu, msr))
++ value = (ia32_mci_value.low) | (ia32_mci_value.high << 32);
++ if value is None:
++ print "CPU 0x%x MSR 0x%x: GPF" % (cpu, msr)
++ else:
++ print "CPU 0x%x MSR 0x%x: 0x%x" % (cpu, msr, value)
++ return value
++
++def test_mce():
++ """Test the existence of machine check errors"""
++
++ """
++ Global capabilities (MCG_CAP) register identifies the capabilities of the
++ machine-check architecture of the processor.
++ """
++ mcg_cap = ia32_rdmsr(MSR_IA32_MCG_CAP)
++
++ """
++ The lower 8 bits specify the number of hardware-unit error-reporting banks
++ present in a particular processor.
++ """
++ nbanks = mcg_cap & 0xff
++ print("Detected %d banks using MCG_CAP = 0x%x" % (nbanks, mcg_cap))
++
++ for j in range(nbanks):
++
++ """
++ Check if the VAL bit(63) in status register is set and if it is set,
++ only then the MISCV and ADDRV is considered valid.
++ """
++ status_reg = ia32_rdmsr(MSR_IA32_MC0_STATUS + 4*(j))
++ status = status_reg & (1 << 63)
++ testsuite.test('Valid bit in Status register should be 0', status == 0)
++ if(status == 0):
++ continue
++
++ print("Machine check bank %d STATUS = 0x%x" % (j, status_reg))
++
++ """
++ check if the MISCV(MCi_MISC register valid (59)bit) is set
++ """
++ status = status_reg & (1 << 59)
++ if (status):
++ misc_reg = ia32_rdmsr(MSR_IA32_MC0_MISC + 4*(j))
++ print("Machine check bank %d MISC = 0x%x" % (j, misc_reg))
++
++ """
++ check if the ADDRV(MCi_ADDR register valid (58)bit) is set
++ """
++ status = status_reg & (1 << 58)
++ if (status):
++ addr_reg = ia32_rdmsr(MSR_IA32_MC0_ADDR + 4*(j))
++ print("Machine Check bank %d ADDR = 0x%x" % (j, addr_reg))
++
++ return 0
+--
+2.7.4
+
diff --git a/meta-luv/recipes-bsp/bits/bits_git.bb b/meta-luv/recipes-bsp/bits/bits_git.bb
index 45a5de643a1b..8bd621d9d542 100644
--- a/meta-luv/recipes-bsp/bits/bits_git.bb
+++ b/meta-luv/recipes-bsp/bits/bits_git.bb
@@ -61,6 +61,7 @@ SRC_URI = "gitsm://github.com/biosbits/bits.git;protocol=http \
file://libffi-fix-switch-fallthrough-cases-with-GCC7.patch \
file://PYTHON-Fix-switch-fallthrough-cases-with-GCC7.patch \
file://BITS-toplevel.cfg-Disable-Bits-when-user-chose-not-to-run.patch \
+ file://BITS-init.py-Add-a-new-unittest-MCE-tests-to-BITS.patch \
"
S = "${WORKDIR}/git"
--
2.7.4
3 years, 10 months
[PATCH v6 0/3] Configure LUV to enable/disable testsuites independently
by Gayatri Kammela
Hi,
This patch series will configure all the testsuites which will leave the user
a choice of running only specific testsuite(s) if needed. Since all the
testsuites are enabled by default, user needs to explicitly remove the
keyword(s) in luv.cfg file representing the target testsuite(s) to disable.
Changes since v1:
1)Added patch that configure the bits testsuite
Changes since v2:
1)Added support for ARM architecture as well.
Changes since v3:
1)Rebased against luv-2.2-rc2
Changes since v4:
1)Fixed bug in bits patch
Changes since v5:
1)Fixed the issue of missing 'pstore-tests' in append_aarch64 line
2)Updated README file
Gayatri Kammela (3):
luv-tests: Design/build LUV such that each testsuite is enabled or
disabled independently.
Bits: Skip the BITS testsuite if and when needed
Meta-luv/README: Update the README file on the new parameter
"LUV_TESTS"
meta-luv/README | 14 ++++++++++
meta-luv/classes/luv-efi.bbclass | 5 ++++
...g-Disable-Bits-when-user-chose-not-to-run.patch | 31 ++++++++++++++++++++++
meta-luv/recipes-bsp/bits/bits_git.bb | 1 +
meta-luv/recipes-core/images/luv-image.inc | 3 +++
.../luv-test/luv-test/luv-test-manager | 6 +++++
6 files changed, 60 insertions(+)
create mode 100644 meta-luv/recipes-bsp/bits/bits/BITS-toplevel.cfg-Disable-Bits-when-user-chose-not-to-run.patch
--
2.7.4
3 years, 10 months
[PATCH] linux-yocto-efi-test: Add Cavium Saber config
by Naresh Bhat
The linux-yocto-efi-test kernel by default config CONFIG_NR_CPUS=64
Because of this kernel is bringings up only 64 CPUs. But the Cavium's
Saber machine has 28 physical cores on each node with 4 hyperthreads
to each physical core. So, basically kernel should bring up 224 CPUs.
Signed-off-by: Naresh Bhat <naresh.bhat(a)linaro.org>
---
meta-luv/recipes-kernel/linux/linux-yocto-efi-test/qemuarm64/saber.cfg | 1 +
meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb | 1 +
2 files changed, 2 insertions(+)
create mode 100644 meta-luv/recipes-kernel/linux/linux-yocto-efi-test/qemuarm64/saber.cfg
diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/qemuarm64/saber.cfg b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/qemuarm64/saber.cfg
new file mode 100644
index 0000000..0c4b1d9
--- /dev/null
+++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/qemuarm64/saber.cfg
@@ -0,0 +1 @@
+CONFIG_NR_CPUS=256
diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
index faa9c6a..043c96c 100644
--- a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
+++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
@@ -103,6 +103,7 @@ SRC_URI_append_x86-64 = "${COMMON_CFG_x86} \
"
SRC_URI_append_aarch64 = " file://qemuarm64/network.cfg \
file://qemuarm64/sbbr.cfg \
+ file://qemuarm64/saber.cfg \
"
# pstore, highmem and efi configs are common to all the supported architectures
--
2.7.4
3 years, 10 months
[PATCH] grub: Change default tsc calibration method to pmtimer on EFI systems
by Sai Praneeth Prakhya
From: Sai Praneeth <sai.praneeth.prakhya(a)intel.com>
The following grub patch is needed because presently grub hangs on Intel
Soc systems which use 8254 timer to calibrate TSC. This patch makes
pmtimer default instead of 8254 timer. This patch has already been
upstreamed to grub but is not a part of grub 2.02 (present version of
grub used by LUV). So, let's carry this patch in LUV until it's
released in some newer grub version.
Cc: Naresh Bhat <naresh.bhat(a)linaro.org>
Cc: Megha Dey <megha.dey(a)linux.intel.com>
Cc: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
Signed-off-by: Sai Praneeth Prakhya <sai.praneeth.prakhya(a)intel.com>
---
...default-tsc-calibration-method-to-pmtimer.patch | 32 ++++++++++++++++++++++
meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend | 1 +
2 files changed, 33 insertions(+)
create mode 100644 meta-luv/recipes-bsp/grub/files/0001-tsc-Change-default-tsc-calibration-method-to-pmtimer.patch
diff --git a/meta-luv/recipes-bsp/grub/files/0001-tsc-Change-default-tsc-calibration-method-to-pmtimer.patch b/meta-luv/recipes-bsp/grub/files/0001-tsc-Change-default-tsc-calibration-method-to-pmtimer.patch
new file mode 100644
index 000000000000..d61d87d9206e
--- /dev/null
+++ b/meta-luv/recipes-bsp/grub/files/0001-tsc-Change-default-tsc-calibration-method-to-pmtimer.patch
@@ -0,0 +1,32 @@
+From 446794de8da4329ea532cbee4ca877bcafd0e534 Mon Sep 17 00:00:00 2001
+From: "David E. Box" <david.e.box(a)linux.intel.com>
+Date: Fri, 15 Sep 2017 15:37:05 -0700
+Subject: [PATCH] tsc: Change default tsc calibration method to pmtimer on EFI
+ systems
+
+On efi systems, make pmtimer based tsc calibration the default over the
+pit. This prevents Grub from hanging on Intel SoC systems that power gate
+the pit.
+
+Signed-off-by: David E. Box <david.e.box(a)linux.intel.com>
+Reviewed-by: Daniel Kiper <daniel.kiper(a)oracle.com>
+---
+ grub-core/kern/i386/tsc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/grub-core/kern/i386/tsc.c b/grub-core/kern/i386/tsc.c
+index 2e85289d8489..f266eb13185f 100644
+--- a/grub-core/kern/i386/tsc.c
++++ b/grub-core/kern/i386/tsc.c
+@@ -68,7 +68,7 @@ grub_tsc_init (void)
+ #ifdef GRUB_MACHINE_XEN
+ (void) (grub_tsc_calibrate_from_xen () || calibrate_tsc_hardcode());
+ #elif defined (GRUB_MACHINE_EFI)
+- (void) (grub_tsc_calibrate_from_pit () || grub_tsc_calibrate_from_pmtimer () || grub_tsc_calibrate_from_efi() || calibrate_tsc_hardcode());
++ (void) (grub_tsc_calibrate_from_pmtimer () || grub_tsc_calibrate_from_pit () || grub_tsc_calibrate_from_efi() || calibrate_tsc_hardcode());
+ #elif defined (GRUB_MACHINE_COREBOOT)
+ (void) (grub_tsc_calibrate_from_pmtimer () || grub_tsc_calibrate_from_pit () || calibrate_tsc_hardcode());
+ #else
+--
+2.1.4
+
diff --git a/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend b/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
index de68f3d6140e..3cbd79581e77 100644
--- a/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
+++ b/meta-luv/recipes-bsp/grub/grub-efi_2.02.bbappend
@@ -27,6 +27,7 @@ SRC_URI += "file://0001-pe32.h-add-header-structures-for-TE-and-DOS-executab.pat
file://0012-grub-core-loader-add-support-for-memdisks.patch \
file://0013-grub-core-loader-pass-current-disk-device-to-loaded-.patch \
file://0014-grub-util-set-prefix-to-EFI-BOOT-when-booting-f.patch \
+ file://0001-tsc-Change-default-tsc-calibration-method-to-pmtimer.patch \
"
GRUB_BUILDIN = "boot linux ext2 fat serial part_msdos part_gpt \
--
2.1.4
3 years, 10 months
Re: [Luv] [PATCH] linux-yocto-efi-test: x86/mttr: Update only valid variable-range MTRRs
by Megha Dey
On Mon, 2017-11-27 at 21:59 -0800, Ni, Ruiyu wrote:
> Ricardo,
> Thanks for the quick follow up.
> Reviewed-by: Ruiyu Ni <ruiyu.ni(a)intel.com>
Thanks, applied!
>
> Thanks/Ray
>
> > -----Original Message-----
> > From: Ricardo Neri [mailto:ricardo.neri-calderon@linux.intel.com]
> > Sent: Tuesday, November 28, 2017 8:46 AM
> > To: Dey, Megha <megha.dey(a)intel.com>
> > Cc: luv(a)lists.01.org; Song, BinX <binx.song(a)intel.com>; Ricardo Neri
> > <ricardo.neri-calderon(a)linux.intel.com>; Ni, Ruiyu <ruiyu.ni(a)intel.com>
> > Subject: [PATCH] linux-yocto-efi-test: x86/mttr: Update only valid variable-
> > range MTRRs
> >
> > Both the Intel 64 and IA-32 Architectures Software Developer's Manual Vol.
> > 3 in section 11.11 and the AMD Architecture Programmer's Manual Vol. 2 in
> > section 7.7.5 state that in a multi-processor system Memory-Type
> > Range Registers (MTRRs) must provide a type of memory caching for all the
> > physical memory in the system that is consistent across all the processors.
> >
> > For the specific case of the variable-range MTRRs, this implies that their
> > values should be the same across all processors.
> >
> > Variable-range MTRRs utilize a pair of registers, MTRRphysMask_MSR and
> > MTRRphysBase_MSR, to describe the base, range and type of cache used for
> > a
> > memory region. Also, a Valid bit is included in MTRRphysMask_MSR to
> > enable
> > or disable a variable-range MTRR pair.
> >
> > Hence, the condition of consistency across processors described above
> > applies to variable-range MTRRs that are enabled. Disabled variable-range
> > MTTR pairs can be inconsistent as long as they remain disabled.
> >
> > Thus, when a variable-range MTRR pair is disabled, it is not necessary to
> > update MTRRphysBase_MSR as it will not be used. MTRRphysMask_MSR
> > must be
> > updated in all cases as it contains the Valid bit that enables or disables
> > the pair.
> >
> > Also, we want to warn about inconsistent MTRRs settings from BIOS. BIOS
> > might have configured only variable-range MTRR pairs that are enabled.
> > Such optimization was recently implemented in Tianocore: 9c8c4478cfca
> > ("UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid")
> >
> > Thus, report updates to inconsistent pairs only when the pair remains valid
> > after the update or the update resulted in a change of the enabled state
> > (i.e., the pair transitioned from enabled to disabled, or viceversa).
> >
> > This fixes Github issue https://github.com/01org/luv-yocto/issues/127.
> >
> > Cc: Ruiyu Ni <ruiyu.ni(a)intel.com>
> > Reported-by: Bin Song <binx.song(a)intel.com>
> > Signed-off-by: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
> > ---
> > This patch will be submitted to the Linux kernel mailing list. For now,
> > I submit to LUV to ensure this change is present in our upcoming release.
> > Also, details on the update to Tianocore can be found here:
> >
> > https://github.com/tianocore/edk2/commit/9c8c4478cfcacaf5fd60b75ff78d2
> > 6732d93a5b8
> > ---
> > ...tr-Update-only-valid-variable-range-MTRRs.patch | 108
> > +++++++++++++++++++++
> > .../linux/linux-yocto-efi-test_4.14.bb | 1 +
> > 2 files changed, 109 insertions(+)
> > create mode 100644 meta-luv/recipes-kernel/linux/linux-yocto-efi-
> > test/0001-x86-mttr-Update-only-valid-variable-range-MTRRs.patch
> >
> > diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/0001-x86-mttr-
> > Update-only-valid-variable-range-MTRRs.patch b/meta-luv/recipes-
> > kernel/linux/linux-yocto-efi-test/0001-x86-mttr-Update-only-valid-variable-
> > range-MTRRs.patch
> > new file mode 100644
> > index 0000000..0e0fa99
> > --- /dev/null
> > +++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test/0001-x86-mttr-
> > Update-only-valid-variable-range-MTRRs.patch
> > @@ -0,0 +1,108 @@
> > +From b84de8808b34a162cc803bb0e84faa080923edc5 Mon Sep 17 00:00:00
> > 2001
> > +From: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
> > +Date: Tue, 21 Nov 2017 17:30:59 -0800
> > +Subject: [PATCH] x86/mttr: Update only valid variable-range MTRRs
> > +
> > +Both the Intel 64 and IA-32 Architectures Software Developer's Manual Vol.
> > +3 in section 11.11 and the AMD Architecture Programmer's Manual Vol. 2 in
> > +section 7.7.5 state that in a multi-processor system Memory-Type
> > +Range Registers (MTRRs) must provide a type of memory caching for all the
> > +physical memory in the system that is consistent across all the processors.
> > +
> > +For the specific case of the variable-range MTRRs, this implies that their
> > +values should be the same across all processors.
> > +
> > +Variable-range MTRRs utilize a pair of registers, MTRRphysMask_MSR and
> > +MTRRphysBase_MSR, to describe the base, range and type of cache used
> > for a
> > +memory region. Also, a Valid bit is included in MTRRphysMask_MSR to
> > enable
> > +or disable a variable-range MTRR pair.
> > +
> > +Hence, the condition of consistency across processors described above
> > +applies to variable-range MTRRs that are enabled. Disabled variable-range
> > +MTTR pairs can be inconsistent as long as they remain disabled.
> > +
> > +Thus, when a variable-range MTRR pair is disabled, it is not necessary to
> > +update MTRRphysBase_MSR as it will not be used. MTRRphysMask_MSR
> > must be
> > +updated in all cases as it contains the Valid bit that enables or disables
> > +the pair.
> > +
> > +Also, we want to warn about inconsistent MTRRs settings from BIOS. BIOS
> > +might have configured only variable-range MTRR pairs that are enabled.
> > +Thus, report updates to inconsistent pairs only when the pair remains valid
> > +after the update or the update resulted in a change of the enabled state
> > +(i.e., the pair transitioned from enabled to disabled, or viceversa).
> > +
> > +Cc: Ruiyu Ni <ruiyu.ni(a)intel.com>
> > +Reported-by: Bin Song <binx.song(a)intel.com>
> > +Signed-off-by: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
> > +---
> > + arch/x86/kernel/cpu/mtrr/generic.c | 45
> > ++++++++++++++++++++++++++++++--------
> > + 1 file changed, 36 insertions(+), 9 deletions(-)
> > +
> > +diff --git a/arch/x86/kernel/cpu/mtrr/generic.c
> > b/arch/x86/kernel/cpu/mtrr/generic.c
> > +index fdc5521..581f839 100644
> > +--- a/arch/x86/kernel/cpu/mtrr/generic.c
> > ++++ b/arch/x86/kernel/cpu/mtrr/generic.c
> > +@@ -659,23 +659,50 @@ static bool set_mtrr_var_ranges(unsigned int
> > index, struct mtrr_var_range *vr)
> > + unsigned int lo, hi;
> > + bool changed = false;
> > +
> > +- rdmsr(MTRRphysBase_MSR(index), lo, hi);
> > +- if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
> > +- || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
> > ++ /*
> > ++ * An MTRRphysBase/MTRRphysMask pair is only enabled if the Valid
> > bit
> > ++ * (bit 11) in MTRRphysMask_MSR is set. Otherwise its contents are
> > not
> > ++ * used.
> > ++ *
> > ++ * Always write to the to the MTRRphysMask MSR in order to ensure
> > that
> > ++ * both the Valid setting of MTRR pairs and the configuration of valid
> > ++ * ones are consistent across CPUs.
> > ++ */
> > ++
> > ++ rdmsr(MTRRphysMask_MSR(index), lo, hi);
> > ++
> > ++ /* Compare the non-reserved bits */
> > ++ if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) ||
> > ++ (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
> > + (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
> > ++ mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr-
> > >mask_hi);
> > +
> > +- mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr-
> > >base_hi);
> > +- changed = true;
> > ++ /*
> > ++ * Report a change only in enabed MTRRs pairs; either in the
> > ++ * original or the requested settings. Disabled settings are
> > ++ * not relevant.
> > ++ */
> > ++ if ((lo & _BITUL(11)) || (vr->mask_lo & _BITUL(11)))
> > ++ changed = true;
> > + }
> > +
> > +- rdmsr(MTRRphysMask_MSR(index), lo, hi);
> > ++ /*
> > ++ * If the requested mask in @vr has the Valid bit disabled, it is not
> > ++ * necessary to update the base address of the range. The register
> > pair
> > ++ * will remain disabled.
> > ++ */
> > ++ if (!(vr->mask_lo & _BITUL(11)))
> > ++ return changed;
> > +
> > +- if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
> > +- || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
> > ++ rdmsr(MTRRphysBase_MSR(index), lo, hi);
> > ++
> > ++ if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) ||
> > ++ (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
> > + (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
> > +- mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr-
> > >mask_hi);
> > ++ mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr-
> > >base_hi);
> > + changed = true;
> > + }
> > ++
> > + return changed;
> > + }
> > +
> > +--
> > +2.7.4
> > +
> > diff --git a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
> > b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
> > index faa9c6a..184950e 100644
> > --- a/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
> > +++ b/meta-luv/recipes-kernel/linux/linux-yocto-efi-test_4.14.bb
> > @@ -79,6 +79,7 @@ SRC_URI += "file://0001-PCI-Vulcan-AHCI-PCI-bar-fix-
> > for-Broadcom-Vulcan-earl.pat
> > file://0008-x86-efi-Introduce-
> > EFI_WARN_ON_ILLEGAL_ACCESSES.patch \
> > file://0001-selftests-change-reboot-flag-location.patch \
> > file://0001-pstore-test-remove-log-directory.patch \
> > + file://0001-x86-mttr-Update-only-valid-variable-range-MTRRs.patch \
> > "
> >
> > COMMON_CFG_x86 = " file://qemux86/modules.cfg \
> > --
> > 2.7.4
>
3 years, 10 months
[PATCH] fwts: Fix build warning installed-vs-shipped files
by Sai Praneeth Prakhya
From: Sai Praneeth <sai.praneeth.prakhya(a)intel.com>
FWTS-V17.11.00 adds "bash-completion" support. As a result a new
directory structure (usr/share/bash-completion) is created under FWTS
build directory after building FWTS and thus bitbake warns (as shown
below) that these files are installed and are not being shipped. There
are 3 possible solutions to fix this issue:
1. Build FWTS _without_ bash-completion feature
2. Ship this feature as a part of LUV
3. Remove this directory structure after FWTS is built
FWTS does not support disabling this feature and hence we are left with
option 2 or 3. Shipping this feature might make sense hoping that some
developer (disables splash screen) and might use this feature to debug
ACPI issues with FWTS.
WARNING: fwts-V17.11.00+gitAUTOINC+0ec5075e19-r0 do_package: QA Issue:
fwts: Files/directories were installed but not shipped in any package:
/usr/share/bash-completion
/usr/share/bash-completion/completions
/usr/share/bash-completion/completions/fwts
Please set FILES such that these items are packaged. Alternatively if
they are unneeded, avoid installing them or delete them within
do_install.
fwts: 3 installed and not shipped files. [installed-vs-shipped]
Cc: Alex Hung <alex.hung(a)canonical.com>
Cc: Naresh Bhat <naresh.bhat(a)linaro.org>
Cc: Megha Dey <megha.dey(a)linux.intel.com>
Cc: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
Signed-off-by: Sai Praneeth Prakhya <sai.praneeth.prakhya(a)intel.com>
---
meta-luv/recipes-core/fwts/fwts_git.bb | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta-luv/recipes-core/fwts/fwts_git.bb b/meta-luv/recipes-core/fwts/fwts_git.bb
index a4432c60f783..df7556a9b36b 100644
--- a/meta-luv/recipes-core/fwts/fwts_git.bb
+++ b/meta-luv/recipes-core/fwts/fwts_git.bb
@@ -58,3 +58,4 @@ LUV_TEST_ARGS="-r stdout -q --uefitests --log-format='%owner;%field ' \
FILES_${PN} += "${libdir}/fwts/lib*${SOLIBS}"
FILES_${PN} += "/lib/modules/${KERNEL_VERSION}/extra/efi_runtime.ko"
FILES_${PN}-dev += "${libdir}/fwts/lib*${SOLIBSDEV} ${libdir}/fwts/lib*.la"
+FILES_${PN} += "/usr/share/bash-completion"
--
2.1.4
3 years, 10 months
[PATCH] chipsec: bump to v1.3.5
by Ricardo Neri
Update version and source revision.
Signed-off-by: Ricardo Neri <ricardo.neri-calderon(a)linux.intel.com>
---
meta-luv/recipes-core/chipsec/chipsec_git.bb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/meta-luv/recipes-core/chipsec/chipsec_git.bb b/meta-luv/recipes-core/chipsec/chipsec_git.bb
index ece9f1a..e55e52b 100644
--- a/meta-luv/recipes-core/chipsec/chipsec_git.bb
+++ b/meta-luv/recipes-core/chipsec/chipsec_git.bb
@@ -15,8 +15,8 @@ SRC_URI = "git://github.com/chipsec/chipsec.git \
file://0001-Revert-fix-issue-with-building-driver-on-32bit-syste.patch \
"
-SRCREV="284cf0bed6b89eebb99d8625287bbdb0ca079515"
-PV="1.3.3"
+SRCREV="b0f400a27c296f40b54e6aff1723bd6ab3f654a6"
+PV="1.3.5"
DEPENDS = "virtual/kernel python-core nasm-native python-setuptools-native virtual/${TARGET_PREFIX}gcc-initial"
RDEPENDS_${PN} = "python python-shell python-stringold python-xml \
--
2.7.4
3 years, 10 months
