OPAE on Intel FPGA SoC devices
by Gökçe Aydos
Can OPAE also be utilized on devices where the processor and the FPGA
are interconnected via AXI bus, e.g., Cyclone5 SoC
Gökçe
3 years, 10 months
IOMMU in Xeon+FPGA and the perception of memory by OPAE apps
by Furkan Turan
Hello Dears,
I would like to consult on you about the memory view of AFUs.
In OPAE, fpgaGetIOAddress is declared to get IO address, which is
returned as updating the ioaddr parameter passed to it. A variable for
this parameter in one example code is name as buf_pa, as it will return
the IO address for the buffer and that will be the physical address
"pa". However, in some other examples, e.g. hello_fpga.c, the same
variable is names as iova which basically stands for IO virtual address.
As far as I remember the presentation in FPL2017, it was mentioned that
there is no IOMMU right now; therefore, iova and physical address should
be same things. However, the opae.github.io explains the functions
referring to IOMMU, so maybe Intel has already introduced it. In that
case, AFUs should not work with physical addresses, but indeed have
virtual addresses which will be translated to physical by the IOMMU.
I would like to consult on you about this:
* Is IOMMU available or not?
* If there is IOMMU, then how the page tables are maintained: by OS, or
by OPAE drivers?
* Can this provide the same virtual addresses on both SW and HW side in
the future, making the fpgaGetIOAddress function obsolete?
* May the IOMMU allow getting rid of the contagious memory space
allocation requirement for the buffers in the future?
Kind Regards,
Furkan Turan
3 years, 11 months
